`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/08/10 15:08:51
// Design Name: 
// Module Name: AXI_Lite_Interface
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


interface AXI4_Lite (input logic aclk,input logic aresetn);
//写地址通道
logic awvalid;
logic [31:0]awaddr; 
logic [2:0]awprot; 
logic awready;
//写数据通道
logic wvalid;
logic [31:0] wdata; 
logic [3:0] wstrb;
logic wready;
//写响应通道
logic bready;
logic bvalid;
logic [1:0] bresp;
//读地址通道
logic arvalid;
logic [31:0] araddr; 
logic [2:0] arprot; 
logic arready;
//读数据通道
logic rready;
logic rvalid;
logic [31:0] rdata; 
logic [1:0] rresp;
//modport
modport  Master (
input aclk,aresetn,awready,wready,bvalid,bresp,arready,rvalid,rdata,rresp,
output awvalid,awaddr,awprot,wvalid,wdata,wstrb,bready,arvalid,araddr,arprot,rready
); 
modport Slave (
output awready,wready,bvalid,bresp,arready,rvalid,rdata,rresp,
input aclk,aresetn,awvalid,awaddr,awprot,wvalid,wdata,wstrb,bready,arvalid,araddr,arprot,rready
);
endinterface 

